MOSFET devices are widely used in electronic products. One common example of a MOSFET device is a static random access memory (SRAM) device, which holds binary information. SRAMs are frequently used in the electronics industry, due to their combination of speed, low power, and lack of requirement for refresh.
Standard SRAM cells commonly use cross-coupled inverters, having two N-channel and two P-channel transistors each, accessed by two pass transistors. Such cells are sometimes referred to as “6T” cells, since (with the two pass transistors) they have six transistors per cell, although other configurations are possible (e.g., four pass transistors are used to access the SRAM cell in 2-port memory devices, etc.).
An equivalent circuit for a conventional SRAM circuit is shown in FIG. 1A. As shown in FIG. 1A, the SRAM includes first and second inverters INV1 and INV2, which form a latch, and access transistors TA1 and TA2 for selectively driving the first and second inverters INV1 and INV2. The first inverter INV1 includes a first PMOS transistor TP1 and a first NMOS transistor TN1, and the second inverter INV2 includes a second PMOS transistor TP2 and a second NMOS transistor TN2. The source of each of the first and second PMOS transistors TP1 and TP2 is coupled to a voltage terminal Vdd. The drain of the first PMOS transistor TP1 is coupled to the drain of the first NMOS transistor TN1, while the drain of the second PMOS transistor TP2 is coupled to the drain of the second NMOS transistor TN2. The source of each of the first and second NMOS transistors TN1 and TN2 is coupled to a ground voltage terminal Vss. The gate of the first PMOS transistor TP1 is coupled to that of the first NMOS transistor TN1, and the two gates are coupled to the output terminal S2 of the second inverter INV2, that is, to a common drain between the second PMOS transistor TP2 and the second NMOS transistor TN2. The gate of the second PMOS transistor TP2 is coupled to that of the second NMOS transistor TN2, and the two gates are coupled to the output terminal S1 of the first inverter INV1, that is, to a common drain between the first PMOS transistor TP1 and the first NMOS transistor TN1. The gate of the first access transistor TA1 is coupled to a word line WL, its source is coupled to a bit line BL, and its drain is coupled to the output terminal S1 of the first inverter INV1. Similarly, the gate of the second access transistor TA2 is coupled to the word line WL, its source is coupled to a bit line bar DBL, and its drain is coupled to the output terminal S2 of the second inverter INV2. Here, the bit line bar DBL line carries the inverted BL signal.
In circuits that utilize MOSFET devices, including SRAMs, a gate electrode of one transistor may be directly connected with a neighboring source or drain region of another transistor. If the gate electrode and the source/drain region are closely arranged, a shared contact may be formed for electrical connection, instead of separate contacts. Shared contacts are advantageous, for example, in that a reduction in cell size is generally achieved as the number of contacts decreases.
For example, FIG. 1B illustrates one (of many) possible layouts of an SRAM cell having an equivalent circuit like that of FIG. 1A. FIG. 1B shows access transistors TA1 and TA2, a first inverter including a first PMOS transistor TP1 and a first NMOS transistor TN1, and a second inverter including a second PMOS transistor TP2 and a second NMOS transistor TN2, including various gate regions G1, G2 and drain/source regions D1, D2, D3, D4 corresponding to these transistors. Shared contacts S are also illustrated. FIG. 1B further shows a voltage terminal Vd, ground voltage terminal Vs, word line W, bit line B, and bit line bar DB.
A specific conventional example of a shared contact region of an SRAM cell is shown in schematic cross-section in FIG. 2A. This figure illustrates a semiconductor substrate such as a silicon substrate 10, which contains a P well 12p, an N well 12n, and intervening isolation regions 20. Over the N well 12n is positioned a gate region 34b, which contains a gate conductor and gate insulator (not separately illustrated) and which corresponds, for example, to the gate of transistor TP2 in FIGS. 1A-1B. On either side of the gate region 34b are P-type diffusion regions, 14ps and 14pd, which correspond, for example, to the source and drain regions of transistor TP2 in FIGS. 1A-1B. Over the P well is positioned gate region 34a, which contains a gate conductor and gate insulator and which corresponds, for example, to a shared gate region of transistors TP1 and TN1 in FIGS. 1A-1B. The gate region 34a is connected via shared contact 32s to N-type region 14n, which corresponds, for example, to the drain of transistor TN2 in FIGS. 1A-1B. Shared contact 32s, and well as other contacts 32a, 32b, 32c are provided within insulating layer 30. Contacts 32s, 32a, 32b, 32c, may be created, for example, by forming holes in the dielectric layer 30, and subsequently filling the holes with a metal, such as tungsten. Metal interconnects, such as 42a and 42b are then provided.
The conventional structure shown in FIG. 2A has at least two significant disadvantages. First, as the device shrinks, it becomes more and more difficult to establish shared contacts 32s which reach both the gate 34a and the diffusion region 14n, without experiencing problems in conjunction with alignment, etch stops and metal filling, each of which may adversely affects yield. A second problem is that the metal interconnect region 42a cannot make contact with the shared contact 32s, but rather must be isolated from it by routing the metal interconnect region 42a around the shared contact 32s. This adversely affects area use efficiency.
An alternative approach is shown in FIG. 2B. This approach, like the one of FIG. 2A, has similar problems with respect to alignment, etch stops and metal filling during formation of the shared contact 32s. The second issue of avoiding contact between the metal interconnect region 42a and shared contact 32s, however, is addressed by providing a dielectric layer between them. However, this process requires separate steps for the formation of the shared contact 32s and the other contacts 32a, 32b, 32c, thereby increasing processing costs.